1. Field of the Invention
The present invention relates generally to digital-to-analog converters, and more particularly, to digital-to-analog converters using sigma-delta modulators.
2. Related Art
A preferred technique for achieving accurate analog conversion of digital signals in digital-to-analog converters (DACs) is the noise-shaping technique. This technique makes use of digital signal processing to reduce the required accuracy and complexity of analog components, and by reducing the difficulty of design of these analog components. A noise-shaped sigma-delta DAC includes a digital sigma-delta modulator which quantizes an oversampled digital input signal to a small number of levels. The digital sigma-delta modulator shapes the quantization noise out of the passband of interest. The quantized digital output signal is converted to an analog signal and filtered using analog circuitry. The combination of digital noise shaping and analog filtering reduces the quantization noise to provide an accurate analog representation of the digital input signal.
Complicated linear analog filters are typically required at the output of the sigma-delta DAC to remove the out-of-band quantization noise. If these analog filters are not included then nonlinearities in the signal processing path following the sigma-delta DAC cause the out-of-band noise to intermodulate back into the passband. This reduces the dynamic range of the sigma-delta DAC. A preferred sigma-delta DAC implementation reduces the complexity and difficulty of design of these analog filters by reducing the sensitivity of the design to nonlinearities in analog signal components, and by reducing the required degree of filtering.
Digital sigma-delta modulators require oversampled data which is typically provided by an interpolator. The DAC's input data may be provided at the Nyquist rate and typically requires interpolation to a higher rate before being provided to the sigma-delta modulator. The sigma-delta modulator is clocked using a high-speed digital clock, which is typically much faster than the input data rate provided to the interpolator. In general, noise present near multiples of these clock frequencies does not affect the analog output signal, because these frequencies are well beyond the passband of the signal of interest. However, this noise has a tendency to intermodulate back into the passband when nonlinearities are present in the signal processing path following the sigma-delta DAC.
An exemplary prior art DAC 100 that uses a single bit sigma-delta modulator 142, is discussed with reference to FIG. 1. DAC 100 includes generally an interpolator 141, a sigma-delta modulator 142, and a mixed-mode digital/analog finite impulse response (FIR) filter 143. Interpolator 141 has an input terminal for receiving digital input data 102, a first clock input terminal for receiving a clock signal labeled “CLK1”, a second clock input terminal for receiving a clock signal labeled “CLK2”, and an output terminal for providing an n-bit output signal 104. Interpolator 141 receives digital input data 102 at a first sampling rate (the frequency of CLK1), and provides the n-bit output code 104 at the output thereof at a second, higher sampling rate (the frequency of CLK2) by performing an interpolation between the samples. Input data 102 may already be oversampled as well.
Single bit sigma-delta modulator 142 has an input terminal connected to the output terminal of interpolator 141, a clock input terminal for receiving signal CLK2, and an output terminal for providing output signal 106. Sigma-delta modulator 142 shapes the quantization noise in output signal 106 out-of-band, and thus, output signal 106 is a substantially accurate digital representation of input data 102 within the passband.
FIR filter 143 has an input terminal connected to the output terminal of sigma-delta modulator 142, and an output terminal for providing output signal 108. FIR filter 143 is single-bit, m-stage mixed-mode analog/digital filter that includes m delay elements each with a corresponding analog weighting. Representative delay elements 151, 152, and 153, and representative weighting amplifiers 161, 162, and 163 are illustrated in FIG. 1. Each delay element, labeled “z−1”, has an input terminal connected to a previous delay element, if any, and an output terminal. Amplifiers 161, 162, and 163 have inputs connected to outputs of corresponding delay elements 151, 152, and 153, outputs connected to corresponding positive inputs of a summing device 170, and multiply the inputs thereof to implement FIR filter coefficients labeled “h1”, “h2”, and “hm”, respectively, associated therewith. The coefficient tap weights h1, h2 . . . hm can be set to give a specified frequency response. Analog summing device 170 sums the outputs of all the amplifiers and has an output terminal for providing analog output signal 108 therefrom. Further details of this prior art sigma-delta DAC 100 are described in U.S. Pat. No. 5,323,157, entitled “Sigma-Delta Digital-to-Analog Converter with Reduced Noise” (Ledzius et al.), which is incorporated herein by reference.
Conventional systems, such as the above described prior art DAC 100 suffer from numerous disadvantages. For example, single bit output 106 of sigma-delta modulator 142 has relatively high quantization noise before being filtered by analog FIR filter 143. Therefore, any noise on a reference signal, which could couple from clock frequencies and other high frequency signals, could easily modulate the quantization noise into the signal band.
For example, when the amplitude of the AC component of the digital input signal 102 is small, the quantization error signals within sigma-delta modulator 142 will tend to become periodic; that is, “idle tones” or “limit cycles” are produced. This is a well-known characteristic of sigma delta modulators. Detailed explanation of idle tones and limit cycles is, for example, provided in the book “Delta-Sigma Data Converters—Theory, Design and Simulation,” Norsworthy et. al., IEEE Press, Piscataway, N.J. (1997), which is incorporated herein by reference. The idle tones with largest amplitude are typically produced at frequencies close to one-half of the sample frequency of sigma-delta modulator 142. There are two common causes for these idle tones to fold into the signal passband and degrade the performance of the sigma-delta modulator. One cause is due to interfering digital signals which couple onto the reference voltage for sigma-delta DAC 100. When these interfering digital signals couple onto the reference voltage they intermodulate with the high-frequency quantization noise and cause it to fold into the passband. For this reason sigma-delta DAC 100 is sensitive to coupled digital noise. The second common cause of for the idle tones to fold into the signal passband is due to nonlinearities in the signal processing path at the output of sigma-delta modulator 142. In the presence of these nonlinearities the idle tones typically intermodulate with each other, causing them to fold into the signal passband. Accordingly it would be desirable to filter out the quantization noise related to tones near fs/2.
Another disadvantage of the above described prior art is that the clock frequency of analog FIR filter 143 is the same as the clock frequency of the sigma-delta modulator 142 (i.e., CLK2). Since modulator 142 is highly oversampled in typical applications, analog FIR filter 143 (e.g., including analog summer 170) must operate at a very high clock frequency. Since it typically takes less power and design complexity to operate analog circuitry at lower frequencies, it would be desirable to lower the frequency at which filters and other circuitry must operate.